Associate Professor

Physics of Semiconductor Devices, Nanoelectronics, Semiconductor Device Modeling, Analog & Digital Electronics and Circuits, VLSI Circuits & Systems, Low Power VLSI Design Techniques

1. Nanoelectronics, Compact modeling of advanced CMOS device

2. Novel semiconductor device simulation and modeling, 2D material.

3. Low power digital VLSI systems

4. IC fabrication & Testing.

5. Quantum Computing

1. Ashish Kumar, Md. Waseem Akram, Satya Gopal Dinda, and Bahniman Ghosh “Spin dephasing in silicon germanium (Si1-xGex) nanowires” Journal of Applied Physics, Vol 110, No 11,113720-1 to 113720-7, Dec,2011. DOI : https://doi.org/10.1063/1.3666022

2.  Ashish Kumar, Md. Waseem Akram, Satya Gopal Dinda, and Bahniman Ghosh, “Spin Relaxation in Silicon Nanowires”  Journal of Computational and Theoretical Nanoscience, vol 9, no 11, pp2068-2073,  Dec, 2012.  DOI : https://doi.org/10.1166/jctn.2012.2617

1. Satya Gopal Dinda, Bahniman Ghosh,  “Effect of Spacers on Si Tunneling Field effect  Transistor with P-N-I-N Structure”2013 Annual IEEE India Conference (INDICON). DOI : 10.1109/INDCON.2013.6725856

2. Satya Gopal Dinda, S Sundar Kumar Iyer, “Study of Ambipolar Current of a Steep Slope Tunneling FET with Drain Underlap” 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT). DOI : 10.1109/CONECCT50063.2020.9198344

3. Satya Gopal Dinda, S Sundar Kumar Iyer, “Effect of Temperature on the Electrical Characteristics of All Silicon pnin TFET Device” 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT). DOI : 10.1109/CONECCT50063.2020.9198321

4. Satya Gopal Dinda, S Sundar Kumar Iyer, “Impact of side wall spacer on the performance of double gate steep switching tunnel FET” 2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO 2022). DOI : 10.1109/5NANO53044.2022.9828898

Tunneling Field Effect Transistor simulation & modeling

From January, 2024 to till date as Associate Professor at Saveetha Engineering College, Chennai, Tamilnadu, India.

From March, 2021 to January, 2024 as Associate Professor at Budge Budge Institute of Technology, Kolkata, West Bengal, India.

From May, 2018 to December, 2019 as Contractual Faculty at Maulana Azad National Institute of Technology, Bhopal, Madhya Pradesh, India.

From August, 2008 to July 2010 as Lecturer at College of Engineering and Management, Kolaghat, West Bengal, India.

NA

1.  Organized Webinar as a convener on March 29, 2023 on Solar cell.

1.  Five days Workshop program attended on “Challenges in VLSI: cutting edge perspectives” from 21/07/2008  to 25/07/2008  at Indian Institute of Science, Engineering & Technology Shibpur. Status: Certificate received

2.  Attended International Workshop on the Physics of Semiconductor Devices (IWPSD 2011) from 19/12/2011 to 21/12/2011 held at IIT Kanpur. Status : Certificate received

3.  Faculty development program attended on “Nanoelectronics Devices: Materials to Applications" from 06/12/2021 to 10/12/2021 at Indian Institute of Information Technology Ranchi. Status: Certificate received

4. Participated the FDP  on “Scilab Programme for Engineering Application” from 08/05/2023 to 12/05/2023 conducted by the NITTR Chandigarh. Status : Certificate received

5. Five days Industrial Workshop program attended on “VLSI to System design: Silicon to end Application Approach” from 31/07/2023 to 04/08/2023 organized by AICTE, ARM Education and ST Microelectronics. Status: Certificate received

6. Participated the FDP on  “ECE Lab Practices using Multisim Live Online Simulator” from 4/12/2023 to 8/12/2023 conducted by the NITTR Chandigarh. Status : Certificate received

Sl. No.	Name of Award / Recognition	Awarding Agency	Year
1.	GATE Qualified	MHRD,  Government of India	2006
2.	Institute Assistantship Award	IIT Kanpur	2010
3.	Topper(87%), System Design Through Verilog	NPTEL, IIT Madras	2023
4.	Topper (78%), Physics of Nano Scale Device	NPTEL, IIT Madras	2023